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i#3044 AArch64 SVE codec: Add Bitwise shift, permute and count instrs

Merged Administrator requested to merge i3044-sve-bitwise-shift into master

Created by: joshua-warburton

This patch adds the appropriate macros, tests and codec entries to encode the following variants:

ASR     <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, #<const>
ASR     <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.D
ASR     <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
ASR     <Zd>.<Ts>, <Zn>.<Ts>, #<const>
ASR     <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.D
ASRD    <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, #<const>
ASRR    <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
CLS     <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts>
CLZ     <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts>
CNT     <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts>
LSL     <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, #<const>
LSL     <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.D
LSL     <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
LSL     <Zd>.<Ts>, <Zn>.<Ts>, #<const>
LSL     <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.D
LSLR    <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
LSR     <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, #<const>
LSR     <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.D
LSR     <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
LSR     <Zd>.<Ts>, <Zn>.<Ts>, #<const>
LSR     <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.D
LSRR    <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
RBIT    <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts>

issue: #3044