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  • !5668

i#3544 riscv64, part 3: add instruction set listings

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Merged Administrator requested to merge i3544-riscv64-p3-add-isl into master Sep 30, 2022
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Created by: semihalf-kardach-stanislaw

Add files describing RISC-V instruction encodings for the base spec and each currently ratified extension. Those files are used as a data source by the codec.py generator script.

Currently the prefetch.[irw] instructions (part of Zicbop extension) are commented out as they cause a bug in the trie generation algorithm (due to aliasing encoding of prefetch.[irw] and ori).

Issue #3544

Signed-off-by: Stanislaw Kardach [email protected]

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Source branch: i3544-riscv64-p3-add-isl