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  • DynamoRIO
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  • !5561

i#3544 RFC: Add basic RISC-V definitions

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Merged Administrator requested to merge github/fork/Semihalf/i3544-riscv64-basic-definitions into master Jul 13, 2022
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Created by: semihalf-kardach-stanislaw

This is a first of a set of pull requests whose aim is to enable DynamoRIO compilation for RISC-V architecture.

This change introduces basic architecture specific macro, enum and type definitions that next commits will use. The first commit is separated out of convenience to highlight a potential problem with handling register references in the generic code with multiple architectures. It also highlights an approach which might help with that. The second commit contains the meat of the actual definitions added following (up to my understanding) the existing ARM/Aarch64 approach. This code is not compiled yet (see my branch for a full compilation codebase reference) and should not impact the current X86 and ARM/Aarch32 functionality.

The "RFC" goal of this pull request is to asses whether this approach is proper or maybe a refactoring is required to better accommodate 3 coexisting architectures.

As noted in my comment in the RISC-V feature request issue, this code is not functional and the goal is to first achieve full compilation first and then work on implementing the functionality.

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Source branch: github/fork/Semihalf/i3544-riscv64-basic-definitions