i#5023: AArch64 decode: generate condition flags register r/w marking

This patch adds a new field to codec.txt to make developers explicitly specify whether an instruction touches the condition code register.

For v8.0:

Read only      Write only      Read and write
adc            adds            adcs
bcond          ands            ccmn
csel           bics            ccmp
csinc          fccmp           sbcs
csinv          fccmpe
csneg          fcmp
fcsel          fcmpe
sbc            subs
mrs            msr

Issues: #5023 (closed), #5025 (closed)