Adds evex-promoted opcodes vcvtps2pd, vcvtss2sd, vcvtpd2ps, vcvtsd2ss, vcvtdq2ps, vcvttps2dq, vcvtps2dq, vcvtdq2pd, vcvttpd2dq, vcvtpd2dq, vcvtph2ps, vcvtps2ph.
Adds the new AVX-512 opcodes vcvtpd2udq, vcvtpd2uqq, vcvtps2qq, vcvtps2udq, vcvtps2uqq, vcvttps2udq, vcvttpd2udq, vcvttps2qq, vcvttpd2qq, vcvttps2uqq, vcvttpd2uqq, vcvtss2usi, vcvtsd2usi, vcvttss2usi, vcvttsd2usi, vcvtqq2ps, vcvtqq2pd, vcvtusi2ss, vcvtusi2sd, vcvtudq2ps, vcvtudq2pd, vcvtuqq2ps, vcvtuqq2pd.
Adds tests for above.
Fixes an operand register type for previously added AVX-512 opcodes vcvtss2si vcvtss2si, vcvtsi2ss, vcvtsi2sd, vcvttss2si, vcvttsd2si.
Supports new opcode bytes in fast decoder and fixes random invalid opcode disassembler output in 64-bit test api.dis.
Changes have been tested using a script using api.ir VERBOSE output and the encoded bytes compared against llvm-mc, gas/objdump and capstone (the latter seems to lack support for some instructions). This methodology will be put in a test (xref #3638 ).
Issue: #1312