ARM encoder incorrectly handles VTBL/VTBX reglist in some cases

Created by: egrimley

(This is split off from #2465 (closed).)

Example error message from log (-checklevel 1):

ERROR: from app:  ffb6 69a8  vtbl.8 %d22 %d23 %d24 -> %d6
vs from encoding: ffb6 6aa8  vtbl.8 %d22 %d23 %d24 %d24 -> %d6

It appears from this and other examples that the encoder gets confused when the second source operand (a single register) looks like a continuation of the reglist operand, which is the first source operand. In the case above, the encoder seems to eat d22-d24, then later realise that it needs d24 for the second source operand, but fails to remove d24 from the register list. A search for "greed" in arm/encode.c reveals what the strategy is supposed to be, but apparently it does not work in this case.

(Might other instructions be affected by the same bug?)